Quoting Cristian Ciocaltea (2021-06-10 13:05:23)
> The following clocks of the Actions Semi Owl S500 SoC have been defined
> to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE,
> VDE, BISP, SENSOR[0-1]
>
> There are several issues involved in this approach:
>
> * 'bisp_factor_table[]' describes the configuration of a regular 8-rates
> divider, so its usage is redundant. Additionally, judging by the BISP
> clock context, it is incomplete since it maps only 8 out of 12
> possible entries.
>
> * The clocks mentioned above are not identical in terms of the available
> rates, therefore cannot rely on the same factor table. Specifically,
> BISP and SENSOR* are standard 12-rate dividers so their configuration
> should rely on a proper clock div table, while VCE and VDE require a
> factor table that is a actually a subset of the one needed for DE[1-2]
> clocks.
>
> Let's fix this by implementing the following:
>
> * Add new factor tables 'de_factor_table' and 'hde_factor_table' to
> properly handle DE[1-2], VCE and VDE clocks.
>
> * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1]
> clocks converted to OWL_COMP_DIV.
>
> * Drop the now unused 'bisp_factor_table[]'.
>
> Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since
> there is no reason to always keep ON those clocks.
>
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxx>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
Applied to clk-next
