Hi Rob,
On Wed, Jun 23, 2021 at 4:13 PM Rob Herring <robh@xxxxxxxxxx> wrote:
> On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> > > USB PHY Control bindings
> > >
> > > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > > Add device tree binding document for RZ/G2L USB PHY control driver.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > > + "renesas,rzg2l-usbphyctrl";
> > > > + reg = <0x11c40000 0x10000>;
> > > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > > + power-domains = <&cpg>;
>
> Also, are these all resources of the usbphyctrl block and not just
> resources you happen to want in the driver? For example, the
> power-domain should be the power island that this block resides in.
It's a clock domain, not a power area: the block goes into power-save
mode by stopping the module clock controlled by the CPG.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
