On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote: > Add device tree binding document for RZ/G2L USB PHY control driver. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > V1->V2: > * Add clock properties > --- > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml > > diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml > new file mode 100644 > index 000000000000..8e8ba43f595d > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/renesas,rzg2l-usbphyctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L USB2.0 PHY Control > + > +maintainers: > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > + > +description: > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power down of the > + USB/PHY. > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC} > + - const: renesas,rzg2l-usbphyctrl > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + '#phy-cells': > + # see phy-bindings.txt in the same directory > + const: 1 > + description: | > + The phandle's argument in the PHY specifier is the phy reset control bit > + of usb phy control. > + 0 = Port 1 Phy reset > + 1 = Port 2 Phy reset > + enum: [ 0, 1 ] You already have the const, so this doesn't do anything. > + > +required: > + - compatible > + - reg > + - clocks > + - '#phy-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/r9a07g044-cpg.h> > + > + usbphyctrl@11c40000 { usb-phy@... > + compatible = "renesas,r9a07g044-usbphyctrl", > + "renesas,rzg2l-usbphyctrl"; > + reg = <0x11c40000 0x10000>; > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; > + resets = <&cpg R9A07G044_USB_PCLK>; > + power-domains = <&cpg>; > + #phy-cells = <1>; > + }; > -- > 2.17.1 > >