On 16/06/2021 17:10, Robert Foss wrote:
These changes are ported from the downstream driver, and are used on SM8350
for CAMCC, DISPCC, GCC, GPUCC & VIDEOCC.
Signed-off-by: Robert Foss <robert.foss@xxxxxxxxxx>
---
drivers/clk/qcom/clk-rcg.h | 4 ++++
drivers/clk/qcom/clk-rcg2.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 99efcc7f8d88..a1f05281d950 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -149,6 +149,10 @@ struct clk_rcg2 {
const struct freq_tbl *freq_tbl;
struct clk_regmap clkr;
u8 cfg_off;
+ u8 flags;
+#define FORCE_ENABLE_RCG BIT(0)
+#define HW_CLK_CTRL_MODE BIT(1)
Downstream also has these flags for 8250, but the upstream driver ended
up not using them for the dispcc clocks. Could you please check that you
realy need HW_CLK_CTRL for dispcc clocks?
+#define DFS_SUPPORT BIT(2)
};
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 42f13a2d1cc1..ed2c9b6659cc 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -295,6 +295,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
if (rcg->mnd_width && f->n && (f->m != f->n))
cfg |= CFG_MODE_DUAL_EDGE;
+ if (rcg->flags & HW_CLK_CTRL_MODE)
+ cfg |= CFG_HW_CLK_CTRL_MASK;
+
return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
mask, cfg);
}
--
With best wishes
Dmitry
