Add information about reset gpio for ethernet phy in case someone wants to use it. Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx> --- Changes in v2: None arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 339a12b255c1..5ddcfdf48626 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -204,6 +204,7 @@ phy0: ethernet-phy@21 { ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index d9ad8a4b20d3..f7d718ff116b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xxxxxxxxxx> */ @@ -22,6 +22,7 @@ phyc: ethernet-phy@c { ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; -- 2.32.0