In PCIe driver pipe-clk mux needs to switch between pipe_clk
and XO for GDSC enable. This is done by setting pipe_clk mux
as parent of pipe_clk after phy init.
Signed-off-by: Prasad Malisetty <pmaliset@xxxxxxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8a7a300..5cbbea4 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 {
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
struct clk *pipe_clk;
+ struct clk *pipe_clk_mux;
+ struct clk *pipe_ext_src;
+ struct clk *ref_clk_src;
};
union qcom_pcie_resources {
@@ -1167,6 +1170,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
return ret;
+ if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) {
+ res->pipe_clk_mux = devm_clk_get(dev, "pipe_src");
+ if (IS_ERR(res->pipe_clk_mux))
+ return PTR_ERR(res->pipe_clk_mux);
+
+ res->pipe_ext_src = devm_clk_get(dev, "pipe_ext");
+ if (IS_ERR(res->pipe_ext_src))
+ return PTR_ERR(res->pipe_ext_src);
+
+ res->ref_clk_src = devm_clk_get(dev, "ref");
+ if (IS_ERR(res->ref_clk_src))
+ return PTR_ERR(res->ref_clk_src);
+ }
+
res->pipe_clk = devm_clk_get(dev, "pipe");
return PTR_ERR_OR_ZERO(res->pipe_clk);
}
@@ -1255,6 +1272,11 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+
+ if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280"))
+ clk_set_parent(res->pipe_clk_mux, res->pipe_ext_src);
return clk_prepare_enable(res->pipe_clk);
}
--
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