Quoting Prasad Malisetty (2021-05-21 02:57:00)
> On 2021-05-08 01:36, Stephen Boyd wrote:
> > Quoting Prasad Malisetty (2021-05-07 03:17:27)
> >> Add PCIe controller and PHY nodes for sc7280 SOC.
> >>
> >> Signed-off-by: Prasad Malisetty <pmaliset@xxxxxxxxxxxxxx>
> >> ---
> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 138
> >> +++++++++++++++++++++++++++++++++++
> >> 1 file changed, 138 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> index 2cc4785..a9f25fc1 100644
> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> @@ -12,6 +12,7 @@
> >> #include <dt-bindings/power/qcom-aoss-qmp.h>
> >> #include <dt-bindings/power/qcom-rpmpd.h>
> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> >> +#include <dt-bindings/gpio/gpio.h>
> >>
> >> / {
> >> interrupt-parent = <&intc>;
> >> @@ -316,6 +317,118 @@
> >> };
> >> };
> >>
> > [...]
> >> +
> >> + pcie1_phy: phy@1c0e000 {
> >> + compatible =
> >> "qcom,sm8250-qmp-gen3x2-pcie-phy";
> >> + reg = <0 0x01c0e000 0 0x1c0>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges;
> >> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> >> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> >> + <&gcc GCC_PCIE_CLKREF_EN>,
> >> + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
> >> + clock-names = "aux", "cfg_ahb", "ref",
> >> "refgen";
> >> +
> >> + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> >> + reset-names = "phy";
> >> +
> >> + assigned-clocks = <&gcc
> >> GCC_PCIE1_PHY_RCHNG_CLK>;
> >> + assigned-clock-rates = <100000000>;
> >> +
> >> + status = "disabled";
> >
> > I think the style is to put status disabled close to the compatible?
>
> Generally I have added status disabled in end as like many nodes. just
> curious to ask is there any specific reason to put close to compatible.
It's really up to qcom maintainers, which I am not.
> >> + };
> >> +
> >> + reset-n {
> >> + pins = "gpio2";
> >> + function = "gpio";
> >> +
> >> + drive-strength = <16>;
> >> + output-low;
> >> + bias-disable;
> >> + };
> >> +
> >> + wake-n {
> >> + pins = "gpio3";
> >> + function = "gpio";
> >> +
> >> + drive-strength = <2>;
> >> + bias-pull-up;
> >> + };
> >
> > These last two nodes with the pull-up and drive-strength settings
> > should
> > be in the board files, like the idp one, instead of here in the SoC
> > file. That way board designers can take the SoC and connect the pcie to
> > an external device using these pins and set the configuration they want
> > on these pins, or choose not to connect them to the SoC at all and use
> > those pins for something else.
> >
> > In addition, it looks like the reset could be a reset-gpios property
> > instead of an output-low config.
> >
> we are using reset property as perst gpio in pcie node.
Ok, perst-gpios should be fine. Presumably perst-gpios should be in the
board and not in the SoC because of what I wrote up above.
