On 6/4/2021 7:01 AM, Vladimir Oltean wrote: > From: Vladimir Oltean <vladimir.oltean@xxxxxxx> > > The "reverse RMII" protocol name is a personal invention, derived from > "reverse MII". > > Just like MII, RMII is an asymmetric protocol in that a PHY behaves > differently than a MAC. In the case of RMII, for example: > - the 50 MHz clock signals are either driven by the MAC or by an > external oscillator (but never by the PHY). > - the PHY can transmit extra in-band control symbols via RXD[1:0] which > the MAC is supposed to understand, but a PHY isn't. > > The "reverse MII" protocol is not standardized either, except for this > web document: > https://www.eetimes.com/reverse-media-independent-interface-revmii-block-architecture/# > > In short, it means that the Ethernet controller speaks the 4-bit data > parallel protocol from the perspective of a PHY (it acts like a PHY). > This might mean that it implements clause 22 compatible registers, > although that is optional - the important bit is that its pins can be > connected to an MII MAC and it will 'just work'. > > In this discussion thread: > https://lore.kernel.org/netdev/20210201214515.cx6ivvme2tlquge2@skbuf/ > > we agreed that it would be an abuse of terms to use the "RevMII" name > for anything than the 4-bit parallel MII protocol. But since all the > same concepts can be applied to the 2-bit Reduced MII protocol as well, > here we are introducing a "Reverse RMII" protocol. This means: "behave > like an RMII PHY". > > Signed-off-by: Vladimir Oltean <vladimir.oltean@xxxxxxx> Acked-by: Florian Fainelli <f.fainelli@xxxxxxxxx> -- Florian
