On Wed, May 19, 2021 at 08:26:26PM +0200, Miquel Raynal wrote: > Describe the two reg entries: the first one will receive the > subcontroller configuration, the second one is for the regular cycles on > the memory bus (eg. CMD, ADDR, DATA for a NAND device). > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > --- > .../devicetree/bindings/memory-controllers/pl353-smc.txt | 2 ++ > 1 file changed, 2 insertions(+) This and patch 8 look like 1 change to me (if it stands). > > diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt > index 9d220d4cb39d..d388bb87365f 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt > @@ -6,6 +6,8 @@ of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR). > Required properties: > - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". > - reg : Controller registers map and length. > + First entry is for the configuration registers, > + second entry covers the memory bus transfers. > - clock-names : List of input clock names - "memclk", "apb_pclk" > (See clock bindings for details). > - clocks : Clock phandles (see clock bindings for details). > -- > 2.27.0 >
