Associate operating points with both CPU nodes.
Data source is the shipping TB-RK1808M0 DTB.
Signed-off-by: Andreas Färber <afaerber@xxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk1808.dtsi | 64 ++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
index b4a71c5c8be7..82614c47f144 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
@@ -32,7 +32,10 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
+ dynamic-power-coefficient = <74>;
+ operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -40,6 +43,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
@@ -57,6 +61,66 @@ CPU_SLEEP: cpu-sleep {
};
};
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <800000 800000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <825000 825000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <850000 850000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <875000 875000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <900000 900000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
arm-pmu {
compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
--
2.31.1
