Add the qupv3_id_1 node and the i2c13 child node used for i2c devices
connected to gpio0/gpio1.
Signed-off-by: Jonathan Marek <jonathan@xxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 38 ++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 76a1df371b17..b7b997dd1475 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -468,6 +468,31 @@ uart3: serial@98c000 {
};
};
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_default_state>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
@@ -760,6 +785,19 @@ tx {
function = "qup3";
};
};
+
+ qup_i2c13_default_state: qup-i2c13-default-state {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
rng: rng@10d3000 {
--
2.26.1
