On Tue, May 11, 2021 at 09:48:22AM +0000, Claudiu Manoil wrote: > >-----Original Message----- > >From: Shawn Guo <shawnguo@xxxxxxxxxx> > >Sent: Tuesday, May 11, 2021 6:07 AM > [...] > >Subject: Re: [PATCH] arm64: dts: fsl-ls1028a: Correct ECAM PCIE window > >ranges > > > >+ Claudiu > > > >On Wed, Apr 07, 2021 at 02:34:38PM +0200, Kornel Duleba wrote: > >> Currently all PCIE windows point to bus address 0x0, which does not match > >> the values obtained from hardware during EA. > >> Replace those values with CPU addresses, since in reality we > >> have a 1:1 mapping between the two. > >> > >> Signed-off-by: Kornel Duleba <mindal@xxxxxxxxxxxx> > > > >Claudiu, > > > >Do you have any comment on this? > > > > Well, probing is still working with this change, I've just tested it. > > PCI listing at boot time changes from: > > pci-host-generic 1f0000000.pcie: host bridge /soc/pcie@1f0000000 ranges: > pci-host-generic 1f0000000.pcie: MEM 0x01f8000000..0x01f815ffff -> 0x0000000000 > pci-host-generic 1f0000000.pcie: MEM 0x01f8160000..0x01f81cffff -> 0x0000000000 > > to: > > pci-host-generic 1f0000000.pcie: host bridge /soc/pcie@1f0000000 ranges: > pci-host-generic 1f0000000.pcie: MEM 0x01f8000000..0x01f815ffff -> 0x01f8000000 > pci-host-generic 1f0000000.pcie: MEM 0x01f8160000..0x01f81cffff -> 0x01f8160000 > > and looks reasonable. > Adding Vladimir and Alex just in case. > > Acked-by: Claudiu Manoil <claudiu.manoil@xxxxxxx> Thanks, Claudiu. Kornel, Do we need a Fixes tag for this patch? Shawn
