On 5/4/21 8:49 PM, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of properties > must be kept as they are. > > Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx> > --- > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > new file mode 100644 > index 000000000000..bd014134c322 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > + > +maintainers: > + - Sean Anderson <sean.anderson@xxxxxxxx> > + > +properties: > + compatible: > + items: > + - const: xlnx,axi-timer-2.0 > + - const: xlnx,xps-timer-1.00.a > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: s_axi_aclk > + > + reg: > + maxItems: 1 > + > + xlnx,count-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 8 > + maximum: 32 > + description: > + The width of the counters, in bits. > + > + xlnx,gen0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,gen1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. > + > + xlnx,one-timer-only: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + Whether only one timer is present in this block. > + > + xlnx,trig0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,trig1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. > + Based on xilinx design tool selection there is also mode_64bit option which I expect will be translate to xlnx,mode-64bit [0, 1]. But any coverage of this as bool property should be fine. > +required: > + - compatible > + - clocks > + - reg > + - xlnx,count-width > + - xlnx,gen0-assert > + - xlnx,gen1-assert these 3 shouldn't be required. > + - xlnx,one-timer-only > + - xlnx,trig0-assert > + - xlnx,trig1-assert these 2 are also not required. > + > +additionalProperties: true > + > +examples: > + - | > + axi_timer_0: timer@800e0000 { > + clock-frequency = <99999001>; I can't see this listed above. It is allowed to have additional properties but I don't think it is good to list it here. > + clock-names = "s_axi_aclk"; > + clocks = <&zynqmp_clk 71>; > + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; > + reg = <0x800e0000 0x10000>; > + xlnx,count-width = <0x20>; > + xlnx,gen0-assert = <0x1>; > + xlnx,gen1-assert = <0x1>; > + xlnx,one-timer-only = <0x0>; > + xlnx,trig0-assert = <0x1>; > + xlnx,trig1-assert = <0x1>; > + }; > Thanks, Michal
