From: Michael Grzeschik <m.grzeschik@xxxxxxxxxxxxxx> Microchip SMI0 Mode is a special mode, where the MDIO Read/Write commands are part of the PHY Address and the OP Code is always 0. We add the compatible for this special mode of the bitbanged mdio driver. Cc: devicetree@xxxxxxxxxxxxxxx Reviewed-by: Andrew Lunn <andrew@xxxxxxx> Reviewed-by: Florian Fainelli <f.fainelli@xxxxxxxxx> Acked-by: Rob Herring <robh@xxxxxxxxxx> Signed-off-by: Michael Grzeschik <m.grzeschik@xxxxxxxxxxxxxx> Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx> --- v1 -> v2: - patch not present v2 -> v3: - first patch v3 -> v4: - no changes --- Documentation/devicetree/bindings/net/mdio-gpio.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt index 8dbcf8295c6c..4d91a36c5cf5 100644 --- a/Documentation/devicetree/bindings/net/mdio-gpio.txt +++ b/Documentation/devicetree/bindings/net/mdio-gpio.txt @@ -2,6 +2,7 @@ MDIO on GPIOs Currently defined compatibles: - virtual,gpio-mdio +- microchip,mdio-smi0 MDC and MDIO lines connected to GPIO controllers are listed in the gpios property as described in section VIII.1 in the following order: -- 2.29.2
