On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote: > This patch adds zynqmp afi config driver.This is useful for > the configuration of the PS-PL interface on Zynq US+ MPSoC > platform. Again, please spell out what those terms mean, as I have no idea :( > > Signed-off-by: Nava kishore Manne <nava.manne@xxxxxxxxxx> > --- > drivers/misc/Kconfig | 11 ++++++ > drivers/misc/Makefile | 1 + > drivers/misc/zynqmp-afi.c | 83 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 95 insertions(+) > create mode 100644 drivers/misc/zynqmp-afi.c > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig > index 877b43b3377d..d1ea1eeb3ac1 100644 > --- a/drivers/misc/Kconfig > +++ b/drivers/misc/Kconfig > @@ -456,6 +456,17 @@ config ZYNQ_AFI > between PS and PL, the AXI port data path should be configured > with the proper Bus-width values > > +config ZYNQMP_AFI > + tristate "Xilinx ZYNQMP AFI support" > + help > + ZynqMP AFI driver support for writing to the AFI registers for > + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the > + PS to the programmable logic (PL) through the AXI port. This AXI > + port helps to establish the data path between the PS and PL. > + In-order to establish the proper communication path between > + PS and PL, the AXI port data path should be configured with > + the proper Bus-width values Please use tabs properly, you mix them above, checkpatch should have caught that. thanks, greg k-h
