Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the programmable logic (PL) through the AXI port.This AXI port helps to establish the data path between the PS and PL. In-order to establish to proper communication data path between PS and PL the AXI port data path should be configured with the proper Bus-width values This patch series Adds afi config drivers support to handle the PS-PL AXI port bus-width configurations. Nava kishore Manne (5): misc: doc: Add binding doc for the afi config driver misc: zynq: Add afi config driver firmware: xilinx: Add afi ioctl support misc: doc: Add binding doc for the zynqmp afi config driver misc: zynqmp: Add afi config driver .../bindings/misc/xlnx,zynq-afi-fpga.yaml | 47 ++++++ .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++ drivers/firmware/xilinx/zynqmp.c | 13 ++ drivers/misc/Kconfig | 22 +++ drivers/misc/Makefile | 2 + drivers/misc/zynq-afi.c | 81 +++++++++++ drivers/misc/zynqmp-afi.c | 83 +++++++++++ include/linux/firmware/xlnx-zynqmp.h | 7 + 8 files changed, 391 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml create mode 100644 drivers/misc/zynq-afi.c create mode 100644 drivers/misc/zynqmp-afi.c -- 2.18.0
