On 4/7/2021 1:58 PM, Rob Herring wrote: > On Tue, Mar 09, 2021 at 03:22:41PM +0100, Rafał Miłecki wrote: >> From: Rafał Miłecki <rafal@xxxxxxxxxx> >> >> CRU is a block used in Northstar devices. It can be seen in the >> bcm5301x.dtsi and this binding documents its proper usage. >> >> Signed-off-by: Rafał Miłecki <rafal@xxxxxxxxxx> >> --- >> .../devicetree/bindings/bus/brcm,cru.yaml | 41 +++++++++++++++++++ >> 1 file changed, 41 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/bus/brcm,cru.yaml >> >> diff --git a/Documentation/devicetree/bindings/bus/brcm,cru.yaml b/Documentation/devicetree/bindings/bus/brcm,cru.yaml >> new file mode 100644 >> index 000000000000..c3b1ca53a443 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/bus/brcm,cru.yaml >> @@ -0,0 +1,41 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/bus/brcm,cru.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Broadcom CRU >> + >> +maintainers: >> + - Rafał Miłecki <rafal@xxxxxxxxxx> >> + >> +description: | >> + Broadcom CRU ("Clock and Reset Unit" or "Central Resource Unit") is a hardware >> + block grouping smaller blocks. It contains e.g. clocks, pinctrl, USB PHY and > > Are these really separate blocks? I really need to see a complete > binding for the block. The situation is a bit confusing because the CRU that is being described here is not the CRU that is being described in the datasheet as a block... but the registers are still prefixed CRU because they have a clocking and reset component/function. There are CRU registers within the DMU (Device Management Unit) and the DMU is a sundry of various things containing: - an internal MDIO bus controller (PCU_MDIO_MGT, PCU_MDIO_CMD) - 4 registers to control and show the internal regulator status - a collection of PLL and clock controls from 0x1800_c100 through 0x180_c180 - reset controls - internal MDIO mux - GPIO/pinmux/drive strength controls - switch register interrupts - adaptive voltage scaling registers - gap - crystal control The 0x1d0 size would span all registers mentioned above and end somewhere in the gap between AVS and XTAL. > >> + thermal. >> + >> +allOf: >> + - $ref: /schemas/simple-bus.yaml# > > I don't think this should be a 'simple-bus'. Maybe 'simple-mfd' instead. > >> + >> +properties: >> + compatible: >> + contains: >> + const: brcm,cru > > This should be SoC specific. Yes agreed, brcm,bcm5301x-cru at least sine this is common to all Northstar platforms. -- Florian
