Hi Geert, On Thu, Jul 10, 2014 at 3:12 PM, Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > Hi Harini, > > On Thu, Jul 10, 2014 at 11:31 AM, Harini Katakam > <harinikatakamlinux@xxxxxxxxx> wrote: >>>> + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | >>>> + SPI_TX_DUAL | SPI_TX_QUAD; >>> >>> Your driver advertises Dual/Quad SPI Transfer capabilities, but it doesn't >>> check spi_transfer.[tr]x_nbits? How can it determine when to enable Dual/Quad? >> >> Here the driver is just giving information that the controller support it. >> The MTD layer enables dual/quad based on what the flash supports; quad >> being the first priority >> I understand that the spi core reads rx, tx-bus-width property and >> master support flags and >> performs the necessary checks. > > That's correct: as long as the rx, tx-bus-width properties do not indicate a > Dual or Quad wiring, it won't be used. > > However, based on schematics, someone may set the rx, tx-bus-width properties > to 4, which is correct, as DT describes the hardware. But this will fail to > work. > So I think it's safer not to announce Dual/Quad support in the driver until > the actual driver support is there. > OK. Correct me if I'm wrong but announcing this support in master->flags is just to say the controller supports it - Like Punnaiah mentioned in the other mail, nothing specific needs to be done from the controller driver to enable dual/quad support. This is at the SOC/IP level. I agree it might or might not be supported at board-level. But that's based on the user's hardware. Should master->flags really take this into consideration? BTW, I dint see master->mode_bits being used anywhere at the moment. Regards, Harini -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
