On Fri, Mar 12, 2021 at 07:40:35PM +0800, Hector Yuan wrote: > From: "Hector.Yuan" <hector.yuan@xxxxxxxxxxxx> > > Add devicetree bindings for MediaTek HW driver. > > Signed-off-by: Hector.Yuan <hector.yuan@xxxxxxxxxxxx> > --- > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 127 ++++++++++++++++++++ > 1 file changed, 127 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > new file mode 100644 > index 0000000..0f3ad47 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > @@ -0,0 +1,127 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek's CPUFREQ Bindings > + > +maintainers: > + - Hector Yuan <hector.yuan@xxxxxxxxxxxx> > + > +description: > + CPUFREQ HW is a hardware engine used by MediaTek > + SoCs to manage frequency in hardware. It is capable of controlling frequency > + for multiple clusters. > + > +properties: > + compatible: > + const: mediatek,cpufreq-hw > + > + reg: > + minItems: 1 > + maxItems: 2 > + description: | > + Addresses and sizes for the memory of the > + HW bases in each frequency domain. > + > + "#performance-domain-cells": A common binding schema for this and 'performance-domains' needs to land first. > + description: > + Number of cells in a performance domain specifier. Typically 0 for nodes > + representing a single performance domain and 1 for nodes providing > + multiple performance domains (e.g. performance controllers), but can be > + any value as specified by device tree binding documentation of particular > + provider. > + enum: [ 0, 1 ] > + > +required: > + - compatible > + - reg > + - "#performance-domain-cells" > + > +additionalProperties: true > + > +examples: > + - | > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + performance-domains = <&performance 0>; > + reg = <0x000>; > + }; > + > + cpu1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + performance-domains = <&performance 0>; > + reg = <0x100>; > + }; > + > + cpu2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + performance-domains = <&performance 0>; > + reg = <0x200>; > + }; > + > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + performance-domains = <&performance 0>; > + reg = <0x300>; > + }; > + > + cpu4: cpu@400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + performance-domains = <&performance 1>; Seems a bit odd that a55 and a75 share a perf domain? > + reg = <0x400>; > + }; > + > + cpu5: cpu@500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + performance-domains = <&performance 1>; > + reg = <0x500>; > + }; > + > + cpu6: cpu@600 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + performance-domains = <&performance 1>; > + reg = <0x600>; > + }; > + > + cpu7: cpu@700 { Do we really need to show 8 cores to show how to use this binding? > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + performance-domains = <&performance 1>; > + reg = <0x700>; > + }; > + }; > + > + /* ... */ > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + performance: performance-controller@11bc00 { > + compatible = "mediatek,cpufreq-hw"; > + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; > + > + #performance-domain-cells = <1>; > + }; > + }; > -- > 1.7.9.5 >
