For running the flash in 8D-8D-8D mode at 166 MHz (controller ref clock speed), PHY calibration procedure needs to run to calculate the proper line delays. To perform this calibration, the controller needs to know the location of the pre-determined calibration pattern on the flash. Add a fixed partition table that contains the calibration partition, along with the rest of the partitions for the platform. Also add a nvmem cell that points to the calibration partition. Signed-off-by: Pratyush Yadav <p.yadav@xxxxxx> --- Based on patch https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210305153926.3479-2-p.yadav@xxxxxx/ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 55 +++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 2fee2906183d..6013ebb45517 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -170,6 +170,8 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + nvmem-cells = <&ospi_calibration_data>; + nvmem-cell-names = "calibration"; flash@0{ compatible = "jedec,spi-nor"; @@ -184,6 +186,59 @@ flash@0{ cdns,read-delay = <0>; #address-cells = <1>; #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partiiton@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@0x6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37e0000>; + }; + + calibration_partition: partition@3fe0000 { + compatible = "nvmem-cells"; + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + + ospi_calibration_data: ospi-calibration-cell@0 { + reg = <0x0 0x80>; + }; + }; + }; }; }; -- 2.30.0
