On 21-03-08 08:52, Teresa Remmet wrote:
> Hello Marco,
>
> Am Montag, den 08.03.2021, 09:40 +0100 schrieb Marco Felsch:
> > On 21-03-08 07:40, Heiko Schocher wrote:
> > > enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
> > >
> > > Signed-off-by: Heiko Schocher <hs@xxxxxxx>
> > > ---
> > >
> > > .../dts/freescale/imx8mp-phycore-som.dtsi | 27
> > > +++++++++++++++++++
> > > 1 file changed, 27 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > index 44a8c2337cee4..0284e7a5c6bba 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > > @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
> > > };
> > > };
> > >
> > > +&flexspi {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_flexspi0>;
> > > + status = "okay";
> > > +
> > > + flash0: mt25qu256aba@0 {
> > > + reg = <0>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + compatible = "jedec,spi-nor";
> >
> > Please make the compatible the first property followed by the reg
> > property. Also you don't need to add the #size-cells and #address-
> > cells
> > now since you don't add a child node.
>
> but is this not similar to the label here? If you add partitions in the
> bootloader you need the cells properties?
If the bootloader will add partitions the bootloader can add the
size/address-cells too using the phandle. But this is more a nit.
Regards,
Marco
> Teresa
>
> >
> > Regards,
> > Marco
> >
> > > + spi-max-frequency = <80000000>;
> > > + spi-tx-bus-width = <4>;
> > > + spi-rx-bus-width = <4>;
> > > + };
> > > +};
> > > +
> > > &i2c1 {
> > > clock-frequency = <400000>;
> > > pinctrl-names = "default";
> > > @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15
> > > 0x11
> > > >;
> > > };
> > >
> > > + pinctrl_flexspi0: flexspi0grp {
> > > + fsl,pins = <
> > > + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK
> > > 0x1c2
> > > + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x8
> > > 2
> > > + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x8
> > > 2
> > > + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x8
> > > 2
> > > + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x8
> > > 2
> > > + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x8
> > > 2
> > > + >;
> > > + };
> > > +
> > > pinctrl_i2c1: i2c1grp {
> > > fsl,pins = <
> > > MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x4
> > > 00001c3
> > > --
> > > 2.29.2
> > >
> > >
> > >
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