This patch adds rockchip support in sdhci-of-dwcmhsc.yaml
Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
---
.../devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml | 26 ++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
index 9d717a8..efec5d5 100755
--- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
@@ -16,6 +16,7 @@ allOf:
properties:
compatible:
enum:
+ - rockchip,dwcmshc-sdhci
- snps,dwcmshc-sdhci
reg:
@@ -27,16 +28,26 @@ properties:
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 5
description:
Handle to "core" for core clock and "bus" for optional bus clock.
+ "axi", "block" and "timer" are for Rockchip specified which aims for
+ DMA, pipe and internal timer respectively.
clock-names:
minItems: 1
- maxItems: 2
+ maxItems: 5
items:
- const: core
- const: bus
+ - const: axi
+ - const: block
+ - const: timer
+
+ rockchip,txclk-tapnum:
+ description: Specify the number of delay for tx sampling.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
required:
- compatible
@@ -49,6 +60,17 @@ unevaluatedProperties: false
examples:
- |
+ mmc@fe310000 {
+ compatible = "rockchip,dwcmshc-sdhci";
+ reg = <0xfe310000 0x10000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ - |
mmc@aa0000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xaa000 0x1000>;
--
2.7.4
