On Mon, Jun 30, 2014 at 6:04 PM, Stephen Warren <swarren@xxxxxxxxxxxxx> wrote: > On 06/19/2014 05:37 AM, Thierry Reding wrote: >> From: Thierry Reding <treding@xxxxxxxxxx> >> >> The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads >> that lanes can be assigned to in order to support a variety of interface >> options: USB 2.0, USB 3.0, PCIe and SATA. >> >> In addition to the pin controller used to assign lanes to pads two PHYs >> are exposed to allow the bricks for PCIe and SATA to be powered up and >> down by PCIe and SATA drivers. > > Linus, does the driver look OK? I'm hoping for an ack from you so that I > can take this series through the Tegra tree to resolve some > dependencies; we have various other drivers that depend on this series. Sure thing, if it looks OK to you, by all means apply it yo your tree. Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx> (Also goes for the DT bindings FWIW) Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
