Quoting Daniel Palmer (2020-12-21 00:51:56) > Hi Stephen, > > On Mon, 21 Dec 2020 at 03:44, Stephen Boyd <sboyd@xxxxxxxxxx> wrote: > > > > Quoting Daniel Palmer (2020-12-19 22:35:41) > > > Hi Stephen, > > > > > > On Sun, 20 Dec 2020 at 12:39, Stephen Boyd <sboyd@xxxxxxxxxx> wrote: > > > > > + clock-output-names: > > > > > + minItems: 8 > > > > > + maxItems: 8 > > > > > + description: | > > > > > + This should provide a name for the internal PLL clock and then > > > > > + a name for each of the divided outputs. > > > > > > > > Is this necessary? > > > > > > I found without the names specified in the dt probing of muxes that > > > depend on the outputs but appear earlier didn't work. > > > Also this same PLL layout seems to be used in some other places so > > > eventually I was thinking this driver would get used for those PLLs > > > with different output names. > > > > Still seems like it could be auto-generated based on dev_name() + > > number. > > At one point I had something similar to that where the output names > were generated at probe. > Without the clock outputs listed in the device tree clock muxes that > source clocks from the mpll couldn't probe properly as they couldn't > look up all of their parents if they probed before the mpll. > Maybe I'm doing something wrong there? I couldn't find a way to always > resolve all of the parents or defer the probe of the muxes until the > mpll clocks are registered. > The child clks should be using clk_parent_data to point to the parent clks through DT. That way the name of the clk doesn't matter except for debug purposes.
