Hi Stephen, On Sun, 20 Dec 2020 at 12:39, Stephen Boyd <sboyd@xxxxxxxxxx> wrote: > > + clock-output-names: > > + minItems: 8 > > + maxItems: 8 > > + description: | > > + This should provide a name for the internal PLL clock and then > > + a name for each of the divided outputs. > > Is this necessary? I found without the names specified in the dt probing of muxes that depend on the outputs but appear earlier didn't work. Also this same PLL layout seems to be used in some other places so eventually I was thinking this driver would get used for those PLLs with different output names. Thanks, Daniel
