Add the devicetree binding for the xilinx clocking wizard. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> --- v6: Fix a yaml warning v7: Add vendor prefix speed-grade v8: Fix the warnings .../bindings/clock/xlnx,clocking-wizard.yaml | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 0000000..579bcc1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> + +description: + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +properties: + compatible: + const: xlnx,clocking-wizard + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + xlnx,speed-grade: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Speed grade of the device. + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - speed-grade + +additionalProperties: false + +examples: + - | + clock-generator@40040000 { + #clock-cells = <1>; + reg = <0x40040000 0x1000>; + compatible = "xlnx,clocking-wizard"; + xlnx,speed-grade = <1>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + clock-output-names = "clk_out1", "clk_out2", + "clk_out3", "clk_out4", "clk_out5", + "clk_out6", "clk_out7"; + }; +... -- 2.1.1
