We can use CPU specific pmu configuration to expose the appropriate CPU specific events rather than just the basic generic pmuv3 perf events. Reported-by: Sudeep Holla <sudeep.holla@xxxxxxx> Signed-off-by: Nishanth Menon <nm@xxxxxx> --- AM65: https://pastebin.ubuntu.com/p/TF2cCMySkt/ J721E: https://pastebin.ubuntu.com/p/jgGPNmNgG3/ J7200: https://pastebin.ubuntu.com/p/Kfc3VHHXNB/ Original report: https://lore.kernel.org/linux-arm-kernel/20210119172412.smsjdo2sjzqi5vcn@bogus/ I have'nt split this patch up for fixes tag primarily because the basic functionality works and this is an improvement than a critical fixup to backport for older kernels. arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index d84c0bc05023..a9fc1af03f27 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 { }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 66169bcf7c9a..b7005b803149 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 { }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index cc483f7344af..f0587fde147e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 { }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.25.1.377.g2d2118b814c1
