Hi This series introduces basic support for recently introduced TI K3 AM642x SoC [1] which contains 3 port (2 external ports) CPSW3g module. The CPSW3g integrated in MAIN domain and can be configured in multi port or switch modes. In this series only multi port mode is enabled. The initial version of switchdev support was introduced by Vignesh Raghavendra [2] and work is in progress. The overall functionality and DT bindings are similar to other K3 CPSWxg versions, so DT binding changes are minimal and driver is mostly re-used for TI K3 AM642x CPSW3g. The main difference is that TI K3 AM642x SoC is not fully DMA coherent and instead DMA coherency is supported per DMA channel. Patches 1-2 - DT bindings update Patches 3-4 - Update driver to support changed DMA coherency model Patches 5-6 - adds TI K3 AM642x SoC platform data and so enable CPSW3g [1] https://www.ti.com/lit/pdf/spruim2 [2] https://patchwork.ozlabs.org/project/netdev/cover/20201130082046.16292-1-vigneshr@xxxxxx/ Grygorii Strashko (2): dt-binding: ti: am65x-cpts: add assigned-clock and power-domains props dt-binding: net: ti: k3-am654-cpsw-nuss: update bindings for am64x cpsw3g Peter Ujfalusi (2): net: ethernet: ti: am65-cpsw-nuss: Use DMA device for DMA API net: ethernet: ti: am65-cpsw-nuss: Support for transparent ASEL handling Vignesh Raghavendra (2): net: ti: cpsw_ale: add driver data for AM64 CPSW3g net: ethernet: ti: am65-cpsw: add support for am64x cpsw3g .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 50 ++++++---- .../bindings/net/ti,k3-am654-cpts.yaml | 7 ++ drivers/net/ethernet/ti/am65-cpsw-nuss.c | 96 +++++++++++-------- drivers/net/ethernet/ti/am65-cpsw-nuss.h | 2 + drivers/net/ethernet/ti/cpsw_ale.c | 7 ++ 5 files changed, 101 insertions(+), 61 deletions(-) -- 2.17.1
