Hi, On 12/4/20 7:17 AM, Grygorii Strashko wrote: > > > On 25/11/2020 07:20, Dave Gerlach wrote: >> The AM642 SoC belongs to the K3 Multicore SoC architecture platform, >> providing advanced system integration to enable applications such as >> Motor Drives, PLC, Remote IO and IoT Gateways. >> >> Some highlights of this SoC are: >> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F >> MCUs, and a single Cortex-M4F. >> * Two Gigabit Industrial Communication Subsystems (ICSSG). >> * Integrated Ethernet switch supporting up to a total of two external >> ports. >> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory >> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other >> peripherals. >> * Centralized System Controller for Security, Power, and Resource >> Management (DMSC). >> >> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) >> for further details: https://www.ti.com/lit/pdf/spruim2 >> >> Introduce basic support for the AM642 SoC to enable minimal >> ramdisk boot. Introduce a limited set of MAIN domain periperhals >> under cbass_main and a placeholder cbass_mcu node for future MCU >> domain usage. >> >> Signed-off-by: Dave Gerlach <d-gerlach@xxxxxx> >> --- >> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++ >> arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++ >> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++ >> 3 files changed, 338 insertions(+) >> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> new file mode 100644 >> index 000000000000..4830a8e4d89b >> --- /dev/null >> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> @@ -0,0 +1,178 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for AM642 SoC Family Main Domain peripherals >> + * >> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ >> + */ >> + >> +&cbass_main { >> + gic500: interrupt-controller@1800000 { >> + compatible = "arm,gic-v3"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ >> + <0x00 0x01840000 0x00 0xC0000>; /* GICR */ >> + /* >> + * vcpumntirq: >> + * virtual CPU interface maintenance interrupt >> + */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + >> + gic_its: msi-controller@1820000 { >> + compatible = "arm,gic-v3-its"; >> + reg = <0x00 0x01820000 0x00 0x10000>; >> + socionext,synquacer-pre-its = <0x1000000 0x400000>; >> + msi-controller; >> + #msi-cells = <1>; >> + }; >> + }; >> + >> + dmss { >> + compatible = "simple-mfd"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + dma-ranges; >> + ranges; >> + >> + secure_proxy_main: mailbox@4d000000 { >> + compatible = "ti,am654-secure-proxy"; >> + #mbox-cells = <1>; >> + reg-names = "target_data", "rt", "scfg"; >> + reg = <0x00 0x4d000000 0x00 0x80000>, >> + <0x00 0x4a600000 0x00 0x80000>, >> + <0x00 0x4a400000 0x00 0x80000>; >> + interrupt-names = "rx_012"; >> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; >> + >> + dmsc: dmsc { >> + compatible = "ti,k2g-sci"; >> + ti,host-id = <12>; >> + mbox-names = "rx", "tx"; >> + mboxes= <&secure_proxy_main 12>, >> + <&secure_proxy_main 13>; >> + >> + k3_pds: power-controller { >> + compatible = "ti,sci-pm-domain"; >> + #power-domain-cells = <2>; >> + }; >> + >> + k3_clks: clocks { >> + compatible = "ti,k2g-sci-clk"; >> + #clock-cells = <2>; >> + }; >> + >> + k3_reset: reset-controller { >> + compatible = "ti,sci-reset"; >> + #reset-cells = <2>; >> + }; >> + }; >> + >> + main_pmx0: pinctrl@f4000 { >> + compatible = "pinctrl-single"; >> + reg = <0x00 0xf4000 0x00 0x2e4>; >> + #pinctrl-cells = <1>; >> + pinctrl-single,register-width = <32>; >> + pinctrl-single,function-mask = <0xffffffff>; >> + }; >> + >> + chipid@43000014 { >> + compatible = "ti,am654-chipid"; >> + reg = <0x00 0x43000014 0x00 0x4>; >> + }; > > Could you add proper syscon node for CTRL_MMR and place chipid under it, pls? Sure this is no problem for v2, will do. Regards, Dave
