Silvaco provide a dual-role I3C master. Description is rather simple: it needs a register mapping, three clocks and an interrupt. Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> --- .../bindings/i3c/silvaco,i3c-master.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml diff --git a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml new file mode 100644 index 000000000000..509de48455b0 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silvaco I3C master + +maintainers: + - Conor Culhane <conor.culhane@xxxxxxxxxxx> + +properties: + compatible: + const: silvaco,i3c-master + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: pclk, the system clock + - description: fast_clk, for the bus + - description: slow_clk, for other events + + clock-names: + minItems: 3 + maxItems: 3 + + resets: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + i3c-master@a0000000 { + compatible = "silvaco,i3c-master"; + clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>; + clock-names = "pclk", "fast_clk", "slow_clk"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0xa0000000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; -- 2.20.1
