Hi Adam,
On Mon, Dec 28, 2020 at 3:39 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> On Mon, Dec 28, 2020 at 6:33 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > On Thu, Dec 24, 2020 at 2:53 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> > > On Tue, Dec 22, 2020 at 2:03 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > > On Tue, Dec 22, 2020 at 2:39 AM Adam Ford <aford173@xxxxxxxxx> wrote:
> > > > > On Fri, Dec 18, 2020 at 7:16 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > > > > On Thu, Dec 17, 2020 at 12:52 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> > > > > > > On Thu, Dec 17, 2020 at 2:16 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > > > > > > On Wed, Dec 16, 2020 at 6:03 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> > > > > > > > > On Wed, Dec 16, 2020 at 8:55 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > > > > > > > > On Sun, Dec 13, 2020 at 7:38 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> > > > > > > > > > > When the board was added, clock drivers were being updated done at
> > > > > > > > > > > the same time to allow the versaclock driver to properly configure
> > > > > > > > > > > the modes. Unforutnately, the updates were not applied to the board
> > > > > > > >
> > > > > > > > > > > --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
> > > > > > > > > > > +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
> > > > > > > > > > > @@ -5,6 +5,7 @@
> > > > > > > > > > >
> > > > > > > > > > > #include <dt-bindings/gpio/gpio.h>
> > > > > > > > > > > #include <dt-bindings/input/input.h>
> > > > > > > > > > > +#include <dt-bindings/clk/versaclock.h>
> > > > > > > > > > >
> > > > > > > > > > > / {
> > > > > > > > > > > backlight_lvds: backlight-lvds {
> > > > > > > > > > > @@ -294,12 +295,12 @@ &du_out_rgb {
> > > > > > > > > > > &ehci0 {
> > > > > > > > > > > dr_mode = "otg";
> > > > > > > > > > > status = "okay";
> > > > > > > > > > > - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
> > > > > > > > > > > + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
> > > > > > > > > >
> > > > > > > > > > Why this change? You said before you don't need this
> > > > > > > > > > https://lore.kernel.org/linux-renesas-soc/CAHCN7xJWbP16SA-Ok-5syNnqOZAt8OFJo2_rtg5VrNVsN2-eiQ@xxxxxxxxxxxxxx/
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > > I had talked with the hardware guys about buy pre-programmed
> > > > > > > > > versaclock chips which would have been pre-configured and pre-enabled.
> > > > > > > > > I thought it was going to happen, but it didn't, so we need the
> > > > > > > > > versaclock driver to enable the reference clock for the USB
> > > > > > > > > controllers, ethernet controller and audio clocks. Previously we were
> > > > > > > > > manually configuring it or it was coincidentally working. Ideally,
> > > > > > > > > we'd have the clock system intentionally enable/disable the clocks
> > > > > > > > > when drivers are loaded/unloaded for for power management reasons.
> > > > > > > >
> > > > > > > > Can you tell me how exactly the Versaclock outputs are wired?
> > > > > > >
> > > > > > > The SoC is expecting a fixed external 50 MHz clock connected to
> > > > > > > USB_EXTAL. Instead of a fixed clock, we're using the Versaclock.
> > > > > > > We're also using the Versaclock to drive the AVB TXCRefClk,
> > > > > > > du_dotclkiun0 and du_dotclkin2 (also also called du_dotclkin3 on
> > > > > > > RZ/G2N) instead of fixed clocks.
> > > > > > >
> > > > > > > > E.g. for USB, the bindings don't say anything about a third clock input,
> > > > > > > > so I'd like to know where that clock is fed into USB.
> > > > > > >
> > > > > > > The way the driver is crafted, it can take in multiple clocks and it
> > > > > > > goes through a list to enable them all, so I added the versaclock to
> > > > > > > the array. Without the versaclock reference, the clock doesn't get
> > > > > > > turned on and the USB fails to operate.
> > > > > >
> > > > > > According to the Hardware User's Manual, USBL_EXTAL is used for USB3.0,
> > > > > > while you added the clock references to the EHCI nodes.
> > > > > > Are you sure EHCI is failing without this?
> > >
> > > I talked to a colleague about the USB_EXTAL. He pointed me to table
> > > 60.1 of the RZ/2 Series, 2nd Generate reference manual
> > > (R01UH0808EJ0100 Rev.1.00), which shows the USB EHCI needing the
> > > 50MHz. When I clear out the references from ehci0 and echi1, the USB
> > > stops working, so it does appear that using the versaclock as the 3rd
> > > clock is needed for operating. The device tree bindings for the
> > > generic-ehci provide for up to 4 clocks, so it seems like referencing
> > > clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3> are
> > > not a violation of the bindings.
> >
> > Perhaps you need to use renesas,rcar-usb2-clock-sel?
> > Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml
>
> Thanks for the pointer. I didn't know this existed. It looks like the
> right thing to do. With that node, it appears to enable the
> versaclock and USB works.
> I'll submit a V3 at some point with this node added to each of the
> kit-level files since they use slightly different power-domains.
>
> Do I need to add updates to the bindings for
> renesas,r8a774a1-rcar-usb2-clock-sel; r8a774b1-rcar-usb2-clock-sel;
> and renesas,r8a774e1-rcar-usb2-clock-sel; or I can I just use the
> generic reference to renesas,rcar-gen3-usb2-clock-sel?
Please update the bindings to add support for RZ/G1[MNH].
Note that without doing so, checkpatch will complain when adding the
device nodes to the .dtsi files.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
