Bert, On Sat, 26 Dec 2020 15:02:21 +0000, Bert Vermeulen <bert@xxxxxxxx> wrote: > > On 12/23/20 5:18 PM, Marc Zyngier wrote: > >> + /* Set up interrupt routing */ > >> + writel(RTL8380_IRR0_SETTING, REG(RTL8380_IRR0)); > >> + writel(RTL8380_IRR1_SETTING, REG(RTL8380_IRR1)); > >> + writel(RTL8380_IRR2_SETTING, REG(RTL8380_IRR2)); > >> + writel(RTL8380_IRR3_SETTING, REG(RTL8380_IRR3)); > > > > What is this doing? > > It's fairly evident considering the comments -- routing of secondary > IRQs onto the CPU IRQs. The term "interrupt routing" is normally used when there is multiple possible targets for a given interrupt, in general a SMP system. Given that your toy SoC seems to be UP, using "interrupt routing" in this context is anything *but* evident. Moreover, since this "routing" is obviously SW controlled, how is that going to work when the next system has a different mapping between internal and external interrupts? > But as to packing this into DTS I'm not sure. > > DTS syntax being what it is, this would inevitably get more complex > and harder to understand. Do you have an example where this is done in > a better way? The DT syntax is a lot clearer than the seemingly random bunch of writes above, and has the invaluable advantage of being decoupled from the driver code. If, as I suspect, the same IP block has been copy-pasted across multiple implementations with different interrupt mappings, we'll end up with an explosion of board-specific files, which is exactly the problem DT has been tasked to solve. If the DT model is not suitable for your particular use case, please explain what doesn't work, and people will be more than eager to help. Thanks, M. -- Without deviation from the norm, progress is not possible.
