This describe the new bindings for the added IRQ support in the
pinctrl-microchip-sgpio driver.
Signed-off-by: Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx>
---
.../bindings/pinctrl/microchip,sparx5-sgpio.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
index 08325bf77a81..df0c83cb1c6e 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
@@ -91,6 +91,18 @@ patternProperties:
controlled indirectly by the "ngpios" property: (ngpios/32).
const: 3
+ interrupts:
+ description: Specifies the sgpio IRQ (in parent controller)
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description:
+ Specifies the pin (port and bit) and flags, as defined in
+ defined in include/dt-bindings/interrupt-controller/irq.h
+ const: 3
+
ngpios:
description: The numbers of GPIO's exposed. This must be a
multiple of 32.
@@ -118,6 +130,7 @@ required:
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
sgpio2: gpio@1101059c {
#address-cells = <1>;
#size-cells = <0>;
@@ -134,6 +147,9 @@ examples:
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out2: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
--
2.25.1
