Hello, This series implements support for the MMC core clk-phase-* devicetree bindings in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600 and is present for both the SD/MMC controller and the dedicated eMMC controller. v5 fixes some build issues identified by the kernel test robot. v4 can be found here: https://lore.kernel.org/linux-mmc/20201207142556.2045481-1-andrew@xxxxxxxx/ The series has had light testing on an AST2600-based platform which requires 180deg of input and output clock phase correction at HS200, as well as some synthetic testing under qemu and KUnit. Please review! Cheers, Andrew Andrew Jeffery (6): mmc: core: Add helper for parsing clock phase properties mmc: sdhci-of-aspeed: Expose clock phase controls mmc: sdhci-of-aspeed: Add AST2600 bus clock support mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations MAINTAINERS: Add entry for the ASPEED SD/MMC driver ARM: dts: rainier: Add eMMC clock phase compensation MAINTAINERS | 9 + arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 1 + drivers/mmc/core/host.c | 44 ++++ drivers/mmc/host/Kconfig | 14 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-aspeed-test.c | 100 ++++++++ drivers/mmc/host/sdhci-of-aspeed.c | 251 ++++++++++++++++++- include/linux/mmc/host.h | 17 ++ 8 files changed, 426 insertions(+), 11 deletions(-) create mode 100644 drivers/mmc/host/sdhci-of-aspeed-test.c -- 2.27.0
