On Tue 27 Oct 12:00 CDT 2020, Manivannan Sadhasivam wrote:
> The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on
> SDM845. Hence the support is added reusing the members of ops_2_7_0.
> The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid
> callback, which will be added in successive commit.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Regards,
Bjorn
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index b4761640ffd9..0b180a19b0ea 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1361,6 +1361,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = {
> .post_deinit = qcom_pcie_post_deinit_2_7_0,
> };
>
> +/* Qcom IP rev.: 1.9.0 */
> +static const struct qcom_pcie_ops ops_1_9_0 = {
> + .get_resources = qcom_pcie_get_resources_2_7_0,
> + .init = qcom_pcie_init_2_7_0,
> + .deinit = qcom_pcie_deinit_2_7_0,
> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> + .post_init = qcom_pcie_post_init_2_7_0,
> + .post_deinit = qcom_pcie_post_deinit_2_7_0,
> +};
> +
> static const struct dw_pcie_ops dw_pcie_ops = {
> .link_up = qcom_pcie_link_up,
> };
> @@ -1474,6 +1484,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
> { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
> { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
> + { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
> { }
> };
>
> --
> 2.17.1
>
