On Tue, Nov 10, 2020 at 01:43:26PM +0100, Amelie Delaunay wrote:
> Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format
> using json-schema.
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@xxxxxx>
> ---
> .../bindings/phy/phy-stm32-usbphyc.txt | 73 ----------
> .../bindings/phy/phy-stm32-usbphyc.yaml | 136 ++++++++++++++++++
> 2 files changed, 136 insertions(+), 73 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> deleted file mode 100644
> index 725ae71ae653..000000000000
> --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -STMicroelectronics STM32 USB HS PHY controller
> -
> -The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
> -switch. It controls PHY configuration and status, and the UTMI+ switch that
> -selects either OTG or HOST controller for the second PHY port. It also sets
> -PLL configuration.
> -
> -USBPHYC
> - |_ PLL
> - |
> - |_ PHY port#1 _________________ HOST controller
> - | _ |
> - | / 1|________________|
> - |_ PHY port#2 ----| |________________
> - | \_0| |
> - |_ UTMI switch_______| OTG controller
> -
> -
> -Phy provider node
> -=================
> -
> -Required properties:
> -- compatible: must be "st,stm32mp1-usbphyc"
> -- reg: address and length of the usb phy control register set
> -- clocks: phandle + clock specifier for the PLL phy clock
> -- #address-cells: number of address cells for phys sub-nodes, must be <1>
> -- #size-cells: number of size cells for phys sub-nodes, must be <0>
> -
> -Optional properties:
> -- assigned-clocks: phandle + clock specifier for the PLL phy clock
> -- assigned-clock-parents: the PLL phy clock parent
> -- resets: phandle + reset specifier
> -
> -Required nodes: one sub-node per port the controller provides.
> -
> -Phy sub-nodes
> -==============
> -
> -Required properties:
> -- reg: phy port index
> -- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
> - see phy-bindings.txt in the same directory.
> -- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
> -- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
> -- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
> - port#1 and must be <1> for PHY port#2, to select USB controller
> -
> -
> -Example:
> - usbphyc: usb-phy@5a006000 {
> - compatible = "st,stm32mp1-usbphyc";
> - reg = <0x5a006000 0x1000>;
> - clocks = <&rcc_clk USBPHY_K>;
> - resets = <&rcc_rst USBPHY_R>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - usbphyc_port0: usb-phy@0 {
> - reg = <0>;
> - phy-supply = <&vdd_usb>;
> - vdda1v1-supply = <®11>;
> - vdda1v8-supply = <®18>
> - #phy-cells = <0>;
> - };
> -
> - usbphyc_port1: usb-phy@1 {
> - reg = <1>;
> - phy-supply = <&vdd_usb>;
> - vdda1v1-supply = <®11>;
> - vdda1v8-supply = <®18>
> - #phy-cells = <1>;
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
> new file mode 100644
> index 000000000000..09064bbb68dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
> @@ -0,0 +1,136 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: STMicroelectronics STM32 USB HS PHY controller binding
> +
> +description:
> +
> + The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
> + switch. It controls PHY configuration and status, and the UTMI+ switch that
> + selects either OTG or HOST controller for the second PHY port. It also sets
> + PLL configuration.
> +
> + USBPHYC
> + |_ PLL
> + |
> + |_ PHY port#1 _________________ HOST controller
> + | __ |
> + | / 1|________________|
> + |_ PHY port#2 ----| |________________
> + | \_0| |
> + |_ UTMI switch_______| OTG controller
> +
> +maintainers:
> + - Amelie Delaunay <amelie.delaunay@xxxxxx>
> +
> +properties:
> + compatible:
> + const: st,stm32mp1-usbphyc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +#Required child nodes:
> +
> +patternProperties:
> + "^usb-phy@[0|1]$":
> + type: object
> + description:
> + Each port the controller provides must be represented as a sub-node.
> +
> + properties:
> + reg:
> + description: phy port index.
> + maxItems: 1
> +
> + phy-supply:
> + description: regulator providing 3V3 power supply to the PHY.
> +
> + vdda1v1-supply:
> + description: regulator providing 1V1 power supply to the PLL block
> +
> + vdda1v8-supply:
> + description: regulator providing 1V8 power supply to the PLL block
> +
> + "#phy-cells":
> + enum: [ 0x0, 0x1 ]
> +
> + allOf:
> + - if:
> + properties:
> + reg:
> + const: 0
> + then:
> + properties:
> + "#phy-cells":
> + const: 0
> + else:
> + properties:
> + "#phy-cells":
> + const: 1
> + description:
> + The value is used to select UTMI switch output.
> + 0 for OTG controller and 1 for Host controller.
> +
> + required:
> + - reg
> + - phy-supply
> + - vdda1v1-supply
> + - vdda1v8-supply
> + - "#phy-cells"
additionalProperties: false
With that,
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - "#address-cells"
> + - "#size-cells"
> + - usb-phy@0
> + - usb-phy@1
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/stm32mp1-clks.h>
> + #include <dt-bindings/reset/stm32mp1-resets.h>
> + usbphyc: usbphyc@5a006000 {
> + compatible = "st,stm32mp1-usbphyc";
> + reg = <0x5a006000 0x1000>;
> + clocks = <&rcc USBPHY_K>;
> + resets = <&rcc USBPHY_R>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + usbphyc_port0: usb-phy@0 {
> + reg = <0>;
> + phy-supply = <&vdd_usb>;
> + vdda1v1-supply = <®11>;
> + vdda1v8-supply = <®18>;
> + #phy-cells = <0>;
> + };
> +
> + usbphyc_port1: usb-phy@1 {
> + reg = <1>;
> + phy-supply = <&vdd_usb>;
> + vdda1v1-supply = <®11>;
> + vdda1v8-supply = <®18>;
> + #phy-cells = <1>;
> + };
> + };
> +...
> --
> 2.17.1
>
