Hi Krzysztof, On Wed, 2020-11-11 at 22:33 +0100, Krzysztof Kozlowski wrote: > On Wed, Nov 11, 2020 at 08:38:19PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is as below: > > > > EMI > > | > > M4U > > | > > ------------ > > SMI Common > > ------------ > > | > > +-------+------+------+----------------------+-------+ > > | | | | ...... | | > > | | | | | | > > larb0 larb1 larb2 larb4 ...... larb19 larb20 > > disp0 disp1 mdp vdec IPE IPE > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > mt8192 M4U support 0~16GB iova range. we preassign different engines > > into different iova ranges: > > > > domain-id module iova-range larbs > > 0 disp 0 ~ 4G larb0/1 > > 1 vcodec 4G ~ 8G larb4/5/7 > > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 > > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 > > > > The iova range for CCU0/1(camera control unit) is HW requirement. > > > > Signed-off-by: Yong Wu <yong.wu@xxxxxxxxxxxx> > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > --- [...] > > +#ifndef _DTS_IOMMU_PORT_MT8192_H_ > > +#define _DTS_IOMMU_PORT_MT8192_H_ > > Not accurate header guard. Shoud be: > _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ > > Probably you copied it from some other Mediatek headers - all of them > have header guard pointing to different directory. Thanks very much for your reviewing so many patches. This name like this when it was in the first version. Since it is only used when the consumer devices enable IOMMU, thus called it _IOMMU_PORT... I will use a new patch to rename all of them. > > Best regards, > Krzysztof
