Adds device tree binding documentation for clock gates in the MT7621 SOC. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx> --- .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml new file mode 100644 index 000000000000..89886b066849 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Bus Gates Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx> + +description: | + The MT7621 can gate SoC device clocks. + + Each clock gate is assigned an identifier and client nodes use this identifier + to specify the clock gate which they consume. + + All these identifiers could be found in: + [1]: <include/dt-bindings/clock/mt7621-clk.h>. + +properties: + compatible: + const: mediatek,mt7621-clk + + "#clock-cells": + description: + The first cell indicates the clock gate number, see [1] for available + clocks. + const: 1 + + ralink,sysctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the syscon which is in the same address area with syscon + device. + +required: + - compatible + - '#clock-cells' + - ralink,sysctl + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7621-clk.h> + + clkctrl { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + ralink,sysctl = <&sysc>; + }; -- 2.25.1
