This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS (AHB?). * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. No documentation about a probably existant set of dividers for each ip core is included in the datasheets. So we cannot make anything better, AFAICT. Looking into driver code, there is another frequency which is used in some drivers (uart, sd...) which for any reason is always hardcoded to 50 MHz. Taking this into account this patchset provides three main fixed clocks to the SOC in 'mt7621-pll' which are: - "cpu": with detected frequency (900 MHz in my board). - "ahb": cpu / 4 = 225 Mhz. - "apb": 50 Mhz. PLL controller cannot be manipulatedbecause there is no info about how to do it. Because of this, there is nothing related with registers in the included binding. It also provides a clock gate driver 'mt7621-clk' as a platform driver to allow to enable and disable some clocks in the different ip cores. The parent clocks for this clock gates have also set taking into account existant device tree and driver code resulting in the followings: - "hsdma": "ahb" - "fe": "ahb" - "sp_divtx": "ahb" - "timer": "cpu" - "int": "cpu" - "mc": "ahb" - "pcm": "ahb" - "pio": "ahb" - "gdma": "ahb" - "nand": "ahb" - "i2c": "ahb" - "i2s": "ahb" - "spi": "ahb" - "uart1": "apb" - "uart2": "apb" - "uart3": "apb" - "eth": "ahb" - "pcie0": "ahb" - "pcie1": "ahb" - "pcie2": "ahb" - "crypto": "ahb" - "shxc": "ahb" There was a previous attempt of doing this here[0] but the author did not wanted to make assumptions of a clock plan for the platform. I do really want this to be upstreamed so according to the comments in previous attempt[0] from Oleksij Rempel I have tried to do this by myself. All of this patches have been tested in a GNUBee PC1 resulting in a working platform. [0]: https://www.lkml.org/lkml/2019/7/23/1044 Sergio Paracuellos (7): dt-bindings: clock: add dt binding header for mt7621 clocks dt: bindings: add mt7621-pll device tree binding documentation dt: bindings: add mt7621-clk device tree binding documentation MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621 clk: ralink: add clock gate driver for mt7621 SoC staging: mt7621-dts: make use of new 'mt7621-pll' and 'mt7621-clk' MAINTAINERS: add MT7621 CLOCK maintainer .../bindings/clock/mediatek,mt7621-clk.yaml | 52 ++++ .../bindings/clock/mediatek,mt7621-pll.yaml | 51 ++++ MAINTAINERS | 8 + arch/mips/include/asm/mach-ralink/mt7621.h | 20 ++ arch/mips/ralink/mt7621.c | 87 ++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ralink/Kconfig | 14 + drivers/clk/ralink/Makefile | 2 + drivers/clk/ralink/clk-mt7621.c | 258 ++++++++++++++++++ drivers/staging/mt7621-dts/gbpc1.dts | 11 - drivers/staging/mt7621-dts/mt7621.dtsi | 71 +++-- include/dt-bindings/clock/mt7621-clk.h | 39 +++ 13 files changed, 567 insertions(+), 48 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml create mode 100644 drivers/clk/ralink/Kconfig create mode 100644 drivers/clk/ralink/Makefile create mode 100644 drivers/clk/ralink/clk-mt7621.c create mode 100644 include/dt-bindings/clock/mt7621-clk.h -- 2.25.1
