On Mon, Nov 9, 2020 at 4:25 PM Serge Semin <fancer.lancer@xxxxxxxxx> wrote: > > Hello Damien, > Thanks for your patches. My comments are below. > > On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote: > > Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of > > the ctrlr0 register for SPI masters. The layout of ctrlr0 is: > > > > | 31 .. 23 | 22 .. 21 | 20 .. 16 | > > | other stuff | spi_frf | dfs_32 | > > > > | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | > > | other stuff | tmod | mode | frf | dfs | > > > > > Th main difference of this layout with the 16-bits version is the data > ^ > | > e > > > frame format field which resides in bits 16..20 instead of bits 3..0. > > > > Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the > manual for the 4.0x version of the core, but according to this patch: > https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@xxxxxxxxx/ > it has been ok to use the lowest four bits for DFS setting. Is the commit > message misleading there? 20:16 DFS_32 Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero- padded. 3:0 DFS Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is configured to 16. If SSI_MAX_XFER_SIZE is configured to 32, then writing to this field will not have any effect. As far as I can tell it's an extension to the existing one (which one in use depends on the SSI configuration). The comment you are referring to is about DW_ssi v1.x (vs. DW_apb_ssi v4.x). -- With Best Regards, Andy Shevchenko
