Hello Damien,
Thanks for your patches. My comments are below.
On Sat, Nov 07, 2020 at 05:13:50PM +0900, Damien Le Moal wrote:
> Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of
> the ctrlr0 register for SPI masters. The layout of ctrlr0 is:
>
> | 31 .. 23 | 22 .. 21 | 20 .. 16 |
> | other stuff | spi_frf | dfs_32 |
>
> | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 |
> | other stuff | tmod | mode | frf | dfs |
>
> Th main difference of this layout with the 16-bits version is the data
^
|
e
> frame format field which resides in bits 16..20 instead of bits 3..0.
>
Are you sure they have been moved from [0, 3] to [16, 20]? I don't have the
manual for the 4.0x version of the core, but according to this patch:
https://patchwork.kernel.org/project/spi-devel-general/patch/1575907443-26377-7-git-send-email-wan.ahmad.zainie.wan.mohamad@xxxxxxxxx/
it has been ok to use the lowest four bits for DFS setting. Is the commit
message misleading there?
> Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a
> platform signal that this layout is in use. Modify
> dw_spi_update_config() to test this capability flag to set the data
> frame format field at the correct register location.
>
> Suggested-by: Sean Anderson <seanga2@xxxxxxxxx>
> Signed-off-by: Damien Le Moal <damien.lemoal@xxxxxxx>
> ---
> drivers/spi/spi-dw-core.c | 8 ++++++--
> drivers/spi/spi-dw.h | 9 +++++++++
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index 2e50cc0a9291..841c85247f01 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
> @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
> u32 speed_hz;
> u16 clk_div;
>
> - /* CTRLR0[ 4/3: 0] Data Frame Size */
> - cr0 |= (cfg->dfs - 1);
> + if (!(dws->caps & DW_SPI_CAP_DFS_32))
> + /* CTRLR0[ 4/3: 0] Data Frame Size */
> + cr0 |= (cfg->dfs - 1);
> + else
> + /* CTRLR0[20: 16] Data Frame Size */
> + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET;
If you extend the dfs field from four to five bits, then
controller->bits_per_word_mask field should be properly updated too.
Alas it hasn't been done for the DWC_ssi version of the core. So I suppose it
should be fixed for the both of them.
Just for the record. There are very handy macros for setting and getting bit fields
to/from a variable. This is a good place to use them instead of manually
shifting and defining the offsets. The macros are defined in linux/bitfield.h .
Alas this driver hasn't been converted to using them. So I won't insist on using
them here. But I hope someone will fix it sometime in future...
-Sergey
>
> if (!(dws->caps & DW_SPI_CAP_DWC_SSI))
> /* CTRLR0[ 9:8] Transfer Mode */
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index faf40cb66498..48a11a51a407 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -9,6 +9,7 @@
> #include <linux/io.h>
> #include <linux/scatterlist.h>
> #include <linux/spi/spi-mem.h>
> +#include <linux/bitfield.h>
>
> /* Register offsets */
> #define DW_SPI_CTRLR0 0x00
> @@ -72,6 +73,13 @@
> #define DWC_SSI_CTRLR0_FRF_OFFSET 6
> #define DWC_SSI_CTRLR0_DFS_OFFSET 0
>
> +/*
> + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0.
> + * Based on DW_apb_ssi Databook v4.02a.
> + */
> +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16
> +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16)
> +
> /*
> * For Keem Bay, CTRLR0[31] is used to select controller mode.
> * 0: SSI is slave
> @@ -121,6 +129,7 @@ enum dw_ssi_type {
> #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
> #define DW_SPI_CAP_KEEMBAY_MST BIT(1)
> #define DW_SPI_CAP_DWC_SSI BIT(2)
> +#define DW_SPI_CAP_DFS_32 BIT(3)
>
> /* Slave spi_transfer/spi_mem_op related */
> struct dw_spi_cfg {
> --
> 2.28.0
>
