On Mon, 2020-11-02 at 10:19 -0600, Rob Herring wrote: > On Thu, Oct 29, 2020 at 04:15:10PM +0800, Chuanjia Liu wrote: > > Split the PCIe node and add pciecfg node to fix MSI issue. > > I still think if you are changing the binding this much, then further > work should be done removing the slot nodes. > > > > > Signed-off-by: Chuanjia Liu <chuanjia.liu@xxxxxxxxxxxx> > > Acked-by: Ryder Lee <ryder.lee@xxxxxxxxxxxx> > > --- > > .../bindings/pci/mediatek-pcie-cfg.yaml | 39 ++++++ > > .../devicetree/bindings/pci/mediatek-pcie.txt | 129 +++++++++++------- > > 2 files changed, 118 insertions(+), 50 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml > > new file mode 100644 > > index 000000000000..d3ecbcd032a2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml > > @@ -0,0 +1,39 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek PCIECFG controller > > + > > +maintainers: > > + - Chuanjia Liu <chuanjia.liu@xxxxxxxxxxxx> > > + - Jianjun Wang <jianjun.wang@xxxxxxxxxxxx> > > + > > +description: | > > + The MediaTek PCIECFG controller controls some feature about > > + LTSSM, ASPM and so on. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,generic-pciecfg > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + pciecfg: pciecfg@1a140000 { > > + compatible = "mediatek,generic-pciecfg", "syscon"; > > + reg = <0x1a140000 0x1000>; > > + }; > > +... > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > > index 7468d666763a..c14a2745de37 100644 > > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > > @@ -8,7 +8,7 @@ Required properties: > > "mediatek,mt7623-pcie" > > "mediatek,mt7629-pcie" > > - device_type: Must be "pci" > > -- reg: Base addresses and lengths of the PCIe subsys and root ports. > > +- reg: Base addresses and lengths of the root ports. > > - reg-names: Names of the above areas to use during resource lookup. > > - #address-cells: Address representation for root ports (must be 3) > > - #size-cells: Size representation for root ports (must be 2) > > @@ -143,56 +143,71 @@ Examples for MT7623: > > > > Examples for MT2712: > > > > - pcie: pcie@11700000 { > > + pcie1: pcie@112ff000 { > > compatible = "mediatek,mt2712-pcie"; > > device_type = "pci"; > > - reg = <0 0x11700000 0 0x1000>, > > - <0 0x112ff000 0 0x1000>; > > - reg-names = "port0", "port1"; > > + reg = <0 0x112ff000 0 0x1000>; > > + reg-names = "port1"; > > #address-cells = <3>; > > #size-cells = <2>; > > - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > > - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, > > - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, > > - <&pericfg CLK_PERI_PCIE0>, > > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pcie_irq"; > > + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, > > <&pericfg CLK_PERI_PCIE1>; > > - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; > > - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; > > - phy-names = "pcie-phy0", "pcie-phy1"; > > + clock-names = "sys_ck1", "ahb_ck1"; > > + phys = <&u3port1 PHY_TYPE_PCIE>; > > + phy-names = "pcie-phy1"; > > bus-range = <0x00 0xff>; > > - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; > > + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; > > > > - pcie0: pcie@0,0 { > > - reg = <0x0000 0 0 0 0>; > > + slot1: pcie@1,0 { > > Does the driver still work if this is devfn 0 instead of 1 (or swap 0 > and 1 slots)? I'll bet it does. > The driver still work when devfn 0 instead of 1，but the driver and dtsi need some change.Because some setting in the driver is based on slot number to determine offset. > The reason being is that AFAICT, the Mediatek PCI controller is > Designware based. The registers at 0x70c and 0x73c are DWC 'port logic' > registers. The DWC RC also has a quirk that it doesn't filter config > accesses to only devfn 0 (see pci_dw_valid_device()), so your config > accesses to the RP should work no matter what devfn you use. You'll have > to get rid of the ports list and just get the mtk_pcie_port from > bus->sysdata instead. I don’t understand why must get rid of the ports list and get the mtk_pcie_port from bus->sysdata instead. Ports list was retained for compatibility with the old DTS format. And in pci-tegra.c and pci-mvebu.c ,they also have ports list and devfn doesn't start at 0.(e.g:tegra210.dtsi, armada-385.dtsi). >
