On 20-09-30 17:50:05, Lucas Stach wrote:
> This adds the DT nodes to describe the power domains available on the
> i.MX8MM. Things are a bit more complex compared to other GPCv2 power
> domain setups, as there is now a hierarchy of domains where complete
> subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also
> fine granular gating within those subsystems is possible.
>
> Note that this is still incomplete, as both VPU and DISP domains are
> missing their reset clocks. Those aren't directly sourced from the CCM,
> but have another level of clock gating in the BLKCTL of those domains,
> which needs a separate driver.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 76f040e4be5e..a841fb2d0458 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -4,6 +4,8 @@
> */
>
> #include <dt-bindings/clock/imx8mm-clock.h>
> +#include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/reset/imx8mq-reset.h>
Needs to be imx8mm-reset.h, as in 8MM, not 8MQ.
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -547,6 +549,61 @@
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mm-gpc";
> + reg = <0x303a0000 0x10000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_hsiomix: power-domain@0 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
> + clocks = <&clk IMX8MM_CLK_USB_BUS>;
> + };
> +
> + pgc_pcie: power-domain@1 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_PCIE>;
> + power-domains = <&pgc_hsiomix>;
> + };
> +
> + pgc_otg1: power-domain@2 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_OTG1>;
> + power-domains = <&pgc_hsiomix>;
> + };
> +
> + pgc_otg2: power-domain@3 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_OTG2>;
> + power-domains = <&pgc_hsiomix>;
> + };
> +
> + pgc_gpumix: power-domain@4 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
> + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MM_CLK_GPU_AHB>;
> + };
> +
> + pgc_gpu: power-domain@5 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_GPU>;
> + clocks = <&clk IMX8MM_CLK_GPU_AHB>,
> + <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MM_CLK_GPU2D_ROOT>,
> + <&clk IMX8MM_CLK_GPU3D_ROOT>;
> + resets = <&src IMX8MQ_RESET_GPU_RESET>;
> + power-domains = <&pgc_gpumix>;
> + };
> + };
> + };
> };
>
> aips2: bus@30400000 {
> --
> 2.20.1
>
