> -----Original Message----- > From: Adam Ford [mailto:aford173@xxxxxxxxx] > Sent: Friday, October 23, 2020 9:22 PM > To: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Cc: Shawn Guo <shawnguo@xxxxxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; > Marek Vasut <marex@xxxxxxx>; devicetree <devicetree@xxxxxxxxxxxxxxx>; > Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>; > patchwork-lst@xxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>; Sascha > Hauer <kernel@xxxxxxxxxxxxxx>; Fabio Estevam <festevam@xxxxxxxxx>; > arm-soc <linux-arm-kernel@xxxxxxxxxxxxxxxxxxx> > Subject: Re: [PATCH 10/11] arm64: dts: imx8mm: add GPC node and power > domains > > On Wed, Sep 30, 2020 at 10:55 AM Lucas Stach <l.stach@xxxxxxxxxxxxxx> > wrote: > > > > This adds the DT nodes to describe the power domains available on the > > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > > domain setups, as there is now a hierarchy of domains where complete > > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also fine > > granular gating within those subsystems is possible. > > > > Note that this is still incomplete, as both VPU and DISP domains are > > missing their reset clocks. Those aren't directly sourced from the > > CCM, but have another level of clock gating in the BLKCTL of those > > domains, which needs a separate driver. > > > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 > > +++++++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 76f040e4be5e..a841fb2d0458 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -4,6 +4,8 @@ > > */ > > > > #include <dt-bindings/clock/imx8mm-clock.h> > > +#include <dt-bindings/power/imx8mm-power.h> > > +#include <dt-bindings/reset/imx8mq-reset.h> > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/input/input.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > @@ -547,6 +549,61 @@ > > interrupts = <GIC_SPI 89 > IRQ_TYPE_LEVEL_HIGH>; > > #reset-cells = <1>; > > }; > > + > > + gpc: gpc@303a0000 { > > + compatible = "fsl,imx8mm-gpc"; > > + reg = <0x303a0000 0x10000>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > Does this need an interrupt index within the GIC? > possibly something like: interrupts = <GIC_SPI 87 > IRQ_TYPE_LEVEL_HIGH>; For imx8m, except imx8mq, we don’t use gpc as interrupt controller anymore, the propterty for gic controller etc are redundant, I think BR Jacky Bai > > > > + > > + pgc { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pgc_hsiomix: > power-domain@0 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_HSIOMIX>; > > + clocks = <&clk > IMX8MM_CLK_USB_BUS>; > > + }; > > + > > + pgc_pcie: > power-domain@1 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_PCIE>; > > + power-domains > = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg1: > power-domain@2 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_OTG1>; > > + power-domains > = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg2: > power-domain@3 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_OTG2>; > > + power-domains > = <&pgc_hsiomix>; > > + }; > > + > > + pgc_gpumix: > power-domain@4 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_GPUMIX>; > > + clocks = <&clk > IMX8MM_CLK_GPU_BUS_ROOT>, > > + > <&clk IMX8MM_CLK_GPU_AHB>; > > + }; > > + > > + pgc_gpu: > power-domain@5 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_GPU>; > > + clocks = <&clk > IMX8MM_CLK_GPU_AHB>, > > + > <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + > <&clk IMX8MM_CLK_GPU2D_ROOT>, > > + > <&clk IMX8MM_CLK_GPU3D_ROOT>; > > + resets = <&src > IMX8MQ_RESET_GPU_RESET>; > > + power-domains > = <&pgc_gpumix>; > > + }; > > + }; > > + }; > > }; > > > > aips2: bus@30400000 { > > -- > > 2.20.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists > > .infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=04% > 7C0 > > > 1%7Cping.bai%40nxp.com%7C412f29610c79470d12c408d87756b072%7C68 > 6ea1d3bc > > > 2b4c6fa92cd99c5c301635%7C0%7C0%7C637390561501622327%7CUnknow > n%7CTWFpbG > > > Zsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6 > Mn0% > > > 3D%7C1000&sdata=AazKzk1Tl6LI1hLYGW1xQ%2FEYc8Ad6vk0aBdkJxwu > w3A%3D&a > > mp;reserved=0
