On Thu, Sep 10, 2020 at 04:14:04PM +0530, Sagar Kadam wrote: > Convert device tree bindings for SiFive's PWM controller to YAML > format. > > Signed-off-by: Sagar Kadam <sagar.kadam@xxxxxxxxxx> > --- > .../devicetree/bindings/pwm/pwm-sifive.txt | 33 ---------- > .../devicetree/bindings/pwm/pwm-sifive.yaml | 72 ++++++++++++++++++++++ > 2 files changed, 72 insertions(+), 33 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt > deleted file mode 100644 > index 3d1dd7b0..0000000 > --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt > +++ /dev/null > @@ -1,33 +0,0 @@ > -SiFive PWM controller > - > -Unlike most other PWM controllers, the SiFive PWM controller currently only > -supports one period for all channels in the PWM. All PWMs need to run at > -the same period. The period also has significant restrictions on the values > -it can achieve, which the driver rounds to the nearest achievable period. > -PWM RTL that corresponds to the IP block version numbers can be found > -here: > - > -https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm > - > -Required properties: > -- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". > - Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive > - PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the > - SiFive PWM v0 IP block with no chip integration tweaks. > - Please refer to sifive-blocks-ip-versioning.txt for details. > -- reg: physical base address and length of the controller's registers > -- clocks: Should contain a clock identifier for the PWM's parent clock. > -- #pwm-cells: Should be 3. See pwm.yaml in this directory > - for a description of the cell format. > -- interrupts: one interrupt per PWM channel > - > -Examples: > - > -pwm: pwm@10020000 { > - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; > - reg = <0x0 0x10020000 0x0 0x1000>; > - clocks = <&tlclk>; > - interrupt-parent = <&plic>; > - interrupts = <42 43 44 45>; > - #pwm-cells = <3>; > -}; > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > new file mode 100644 > index 0000000..415d053 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > @@ -0,0 +1,72 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2020 SiFive, Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive PWM controller > + > +maintainers: > + - Yash Shah <yash.shah@xxxxxxxxxx> > + - Sagar Kadam <sagar.kadam@xxxxxxxxxx> > + - Paul Walmsley <paul.walmsley@xxxxxxxxxx> > + > +description: > + Unlike most other PWM controllers, the SiFive PWM controller currently > + only supports one period for all channels in the PWM. All PWMs need to > + run at the same period. The period also has significant restrictions on > + the values it can achieve, which the driver rounds to the nearest > + achievable period. PWM RTL that corresponds to the IP block version > + numbers can be found here - > + > + https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm > + > +properties: > + compatible: > + items: > + - const: sifive,fu540-c000-pwm > + - const: sifive,pwm0 > + description: > + Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported > + compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0 > + as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the > + SiFive PWM v0 IP block with no chip integration tweaks. > + Please refer to sifive-blocks-ip-versioning.txt for details. > + > + reg: > + maxItems: 1 > + description: Physical base address and length of the controller's registers Drop description. > + > + clocks: > + description: Should contain a clock identifier for the PWM's parent clock. How many clocks? > + > + "#pwm-cells": > + const: 3 > + description: > + Should be 3. See pwm.yaml in this directory for a description of the > + cell format. Drop. > + > + interrupts: > + maxItems: 1 Is it 1 or... > + description: One interrupt per PWM channel. one per channel? > + > +required: > + - compatible > + - reg > + - clocks > + - "#pwm-cells" > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + pwm: pwm@10020000 { > + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; > + reg = <0x10020000 0x1000>; > + clocks = <&tlclk>; > + interrupt-parent = <&plic>; > + interrupts = <42 43 44 45>; Split entries: interrupts = <42>, <43>, <44>, <45>; > + #pwm-cells = <3>; > + }; > -- > 2.7.4 >
