On Thu, Sep 10, 2020 at 04:14:03PM +0530, Sagar Kadam wrote: > Convert device tree bindings for SiFive's PLIC to YAML format > > Signed-off-by: Sagar Kadam <sagar.kadam@xxxxxxxxxx> > --- > .../interrupt-controller/sifive,plic-1.0.0.txt | 58 ----------- > .../interrupt-controller/sifive,plic-1.0.0.yaml | 107 +++++++++++++++++++++ > 2 files changed, 107 insertions(+), 58 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt > deleted file mode 100644 > index 6adf7a6..0000000 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt > +++ /dev/null > @@ -1,58 +0,0 @@ > -SiFive Platform-Level Interrupt Controller (PLIC) > -------------------------------------------------- > - > -SiFive SOCs include an implementation of the Platform-Level Interrupt Controller > -(PLIC) high-level specification in the RISC-V Privileged Architecture > -specification. The PLIC connects all external interrupts in the system to all > -hart contexts in the system, via the external interrupt source in each hart. > - > -A hart context is a privilege mode in a hardware execution thread. For example, > -in an 4 core system with 2-way SMT, you have 8 harts and probably at least two > -privilege modes per hart; machine mode and supervisor mode. > - > -Each interrupt can be enabled on per-context basis. Any context can claim > -a pending enabled interrupt and then release it once it has been handled. > - > -Each interrupt has a configurable priority. Higher priority interrupts are > -serviced first. Each context can specify a priority threshold. Interrupts > -with priority below this threshold will not cause the PLIC to raise its > -interrupt line leading to the context. > - > -While the PLIC supports both edge-triggered and level-triggered interrupts, > -interrupt handlers are oblivious to this distinction and therefore it is not > -specified in the PLIC device-tree binding. > - > -While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > -"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > -contains a specific memory layout, which is documented in chapter 8 of the > -SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. > - > -Required properties: > -- compatible : "sifive,plic-1.0.0" and a string identifying the actual > - detailed implementation in case that specific bugs need to be worked around. > -- #address-cells : should be <0> or more. > -- #interrupt-cells : should be <1> or more. > -- interrupt-controller : Identifies the node as an interrupt controller. > -- reg : Should contain 1 register range (address and length). > -- interrupts-extended : Specifies which contexts are connected to the PLIC, > - with "-1" specifying that a context is not present. Each node pointed > - to should be a riscv,cpu-intc node, which has a riscv node as parent. > -- riscv,ndev: Specifies how many external interrupts are supported by > - this controller. > - > -Example: > - > - plic: interrupt-controller@c000000 { > - #address-cells = <0>; > - #interrupt-cells = <1>; > - compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; > - interrupt-controller; > - interrupts-extended = < > - &cpu0-intc 11 > - &cpu1-intc 11 &cpu1-intc 9 > - &cpu2-intc 11 &cpu2-intc 9 > - &cpu3-intc 11 &cpu3-intc 9 > - &cpu4-intc 11 &cpu4-intc 9>; > - reg = <0xc000000 0x4000000>; > - riscv,ndev = <10>; > - }; > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > new file mode 100644 > index 0000000..95c8c85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -0,0 +1,107 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +# Copyright (C) 2020 SiFive, Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive Platform-Level Interrupt Controller (PLIC) > + > +description: > + SiFive SOCs include an implementation of the Platform-Level Interrupt Controller > + (PLIC) high-level specification in the RISC-V Privileged Architecture > + specification. The PLIC connects all external interrupts in the system to all > + hart contexts in the system, via the external interrupt source in each hart. > + > + A hart context is a privilege mode in a hardware execution thread. For example, > + in an 4 core system with 2-way SMT, you have 8 harts and probably at least two > + privilege modes per hart; machine mode and supervisor mode. > + > + Each interrupt can be enabled on per-context basis. Any context can claim > + a pending enabled interrupt and then release it once it has been handled. > + > + Each interrupt has a configurable priority. Higher priority interrupts are > + serviced first. Each context can specify a priority threshold. Interrupts > + with priority below this threshold will not cause the PLIC to raise its > + interrupt line leading to the context. > + > + While the PLIC supports both edge-triggered and level-triggered interrupts, > + interrupt handlers are oblivious to this distinction and therefore it is not > + specified in the PLIC device-tree binding. > + > + While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > + "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > + contains a specific memory layout, which is documented in chapter 8 of the > + SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. > + > +maintainers: > + - Sagar Kadam <sagar.kadam@xxxxxxxxxx> > + - Paul Walmsley <paul.walmsley@xxxxxxxxxx> > + - Palmer Dabbelt <palmer@xxxxxxxxxxx> > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# Don't need this. It gets selected matching on node name. > + > +properties: > + compatible: > + items: > + - const: sifive,plic-1.0.0 > + - const: sifive,fu540-c000-plic Somehow these ended up in the wrong order. Should be most specific to least specific. > + > + description: > + Should be "sifive,plic-1.0.0" and a string identifying the actual > + detailed implementation in case that specific bugs need to be worked around. Drop this. > + > + reg: > + maxItems: 1 > + description: Should contain 1 register range (address and length). Drop this. The schema says this... > + > + '#address-cells': > + const: 0 > + description: Should be <0> or more. Drop. 'or more' is wrong. If there's a case with more, it will need to be documented. > + > + '#interrupt-cells': > + const: 1 > + description: Should be <1> or more. Same here. > + > + interrupt-controller: true > + > + interrupts-extended: > + minItems: 1 > + description: > + Specifies which contexts are connected to the PLIC, with "-1" specifying > + that a context is not present. Each node pointed to should be a > + riscv,cpu-intc node, which has a riscv node as parent. > + > + riscv,ndev: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies how many external interrupts are supported by this controller. > + > +required: > + - compatible > + - '#address-cells' > + - '#interrupt-cells' > + - interrupt-controller > + - reg > + - interrupts-extended > + - riscv,ndev > + > +additionalProperties: false > + > +examples: > + - | > + plic: interrupt-controller@c000000 { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; > + interrupt-controller; > + interrupts-extended = < > + &cpu0_intc 11 > + &cpu1_intc 11 &cpu1_intc 9 > + &cpu2_intc 11 &cpu2_intc 9 > + &cpu3_intc 11 &cpu3_intc 9 > + &cpu4_intc 11 &cpu4_intc 9>; > + reg = <0xc000000 0x4000000>; > + riscv,ndev = <10>; > + }; > -- > 2.7.4 >
