On 10:12-20200917, Tomi Valkeinen wrote:
> Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
> 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.
>
> A slight irregularity in the bindings is the DPTX PHY register block,
> which is in the MHDP IP, but is needed and mapped by the PHY.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
just quick notes below:
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 104 ++++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 12ceea9b3c9a..82d89dd3faf5 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -553,6 +553,82 @@ serdes3: serdes@5030000 {
> };
> };
>
> + serdes_wiz4: wiz@5050000 {
serdes-mux ? - I think we might want to cleanup other similar usage
instead of "wiz" or maybe just "mux"?
> + compatible = "ti,j721e-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + assigned-clocks = <&k3_clks 297 9>;
> + assigned-clock-parents = <&k3_clks 297 10>;
> + assigned-clock-rates = <19200000>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + ranges = <0x5050000 0x0 0x5050000 0x10000>,
> + <0xa030a00 0x0 0xa030a00 0x40>;
> +
> + wiz4_pll0_refclk: pll0-refclk {
clock@ ?
> + clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> + clock-output-names = "wiz4_pll0_refclk";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz4_pll0_refclk>;
> + assigned-clock-parents = <&k3_clks 297 9>;
> + };
> +
> + wiz4_pll1_refclk: pll1-refclk {
same?
> + clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> + clock-output-names = "wiz4_pll1_refclk";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz4_pll1_refclk>;
> + assigned-clock-parents = <&k3_clks 297 9>;
> + };
> +
> + wiz4_refclk_dig: refclk-dig {
same?
> + clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> + clock-output-names = "wiz4_refclk_dig";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz4_refclk_dig>;
> + assigned-clock-parents = <&k3_clks 297 9>;
> + };
> +
> + wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
same?
> + clocks = <&wiz4_refclk_dig>;
> + #clock-cells = <0>;
> + };
> +
> + wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
same?
> + clocks = <&wiz4_pll1_refclk>;
> + #clock-cells = <0>;
> + };
> +
> + serdes4: serdes@5050000 {
> + /*
> + * Note: we also map DPTX PHY registers as the Torrent
> + * needs to manage those.
> + */
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x5050000 0x10000>,
> + <0xa030a00 0x40>; /* DPTX PHY */
> + reg-names = "torrent_phy", "dptx_phy";
> +
> + resets = <&serdes_wiz4 0>;
> + reset-names = "torrent_reset";
> + clocks = <&wiz4_pll0_refclk>;
> + clock-names = "refclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + torrent_phy_dp: phy@0 {
> + reg = <0>;
> + resets = <&serdes_wiz4 1>;
> + cdns,phy-type = <PHY_TYPE_DP>;
> + cdns,num-lanes = <4>;
> + cdns,max-bit-rate = <5400>;
> + #phy-cells = <0>;
> + };
> + };
> + };
> +
Do you see any impact of the discussions we are having at [1] ?
> main_uart0: serial@2800000 {
> compatible = "ti,j721e-uart", "ti,am654-uart";
> reg = <0x00 0x02800000 0x00 0x100>;
> @@ -1024,6 +1100,34 @@ ufs@4e84000 {
> };
> };
>
> + mhdp: dp-bridge@a000000 {
> + compatible = "ti,j721e-mhdp8546";
> + /*
> + * Note: we do not map DPTX PHY area, as that is handled by
> + * the PHY driver.
> + */
> + reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
> + <0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */
> + reg-names = "mhdptx", "j721e-intg";
> +
> + status = "disabled";
> +
> + clocks = <&k3_clks 151 36>;
> +
> + phys = <&torrent_phy_dp>;
> + phy-names = "dpphy";
> +
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> +
> + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
> +
> + dp0_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> dss: dss@04a00000 {
> compatible = "ti,j721e-dss";
> reg =
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
[1] https://lore.kernel.org/linux-devicetree/8a27f8f3-20c4-f72c-b683-81153107d867@xxxxxx/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
