On 06/13/2014 10:18 AM, Tony Lindgren wrote: > * Roger Quadros <rogerq@xxxxxx> [140611 01:58]: >> Since the Interrupt Events are used only by the NAND driver, >> there is no point in managing the Interrupt registers >> in the GPMC driver and complicating it with irqchip modeling. >> >> Let's manage the interrupt registers directly in the NAND driver >> and get rid of irqchip model from GPMC driver. >> >> Get rid of IRQ commands and unused commands from gpmc_configure() in >> the GPMC driver. > > This seems like a step backward to me. The GPMC interrupt enable > register can do edge detection on the wait pins, how is that > limited to NAND? OK. But wait pin edge detection was not yet being used and I couldn't think of how it would ever be used. Any ideas? > > Further, let's not start mixing GPMC hardware module register > access with the NAND driver register access. They can be clocked > separately. And bugs in the NAND driver can cause issues in other > GPMC using drivers. I understood that NAND controller is integrated into the GPMC module and they are clocked the same. Not sure why the hardware designers would keep the registers so closely knit. FYI. memory/ti-amif.c and mtd/nand/davinci_nand.c share the AMIF register space in the same way. I thought it'd be nice to be consistent across TI drivers. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
