On 06/10/2014 05:11 AM, Thierry Reding wrote: > From: Thierry Reding <treding@xxxxxxxxxx> > > The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads > that lanes can be assigned to in order to support a variety of interface > options: USB 2.0, USB 3.0, PCIe and SATA. > > In addition to the pin controller used to assign lanes to pads two PHYs > are exposed to allow the bricks for PCIe and SATA to be powered up and > down by PCIe and SATA drivers. Aside from the issue Andrew pointed out, this series looks good to me. I'll apply once that one issue is fixed. Linus, Patch 2 (pinctrl driver) depends on patch 1 (binding header), and there are other patches that will also depend on the binding header in patch 1. I guess I should apply patch 1 in a topic branch and send you a pull request which you can merge before applying patch 2. Does that sound OK to you? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
