Hi Robert, On Fri, Aug 28, 2020 at 02:13:27PM +0300, Robert Chiras (OSS) wrote: > From: Robert Chiras <robert.chiras@xxxxxxx> > > This patch-set adds the new following features to the nwl-dsi bridge driver: > > 1. Control Video PLL from nwl-dsi driver > > Add support for the Video PLL into the nwl-dsi driver, in order > to better control it's rate, depending on the requested video mode. > Controlling the Video PLL from nwl-dsi is usefull, since it both drives the DC > pixel-clock and DPHY phy_ref clock. > On i.MX8MQ, the DC can be either DCSS or LCDIF. > > 2. Add new property to nwl-dsi: clock-drop-level > > This new property is usefull in order to use DSI panels with the nwl-dsi > driver which require a higher overhead to the pixel-clock. > For example, the Raydium RM67191 DSI Panel works with 132M pixel-clock, > but it needs an overhead in order to work properly. So, the actual pixel-clock > fed into the DSI DPI interface needs to be lower than the one used ad DSI output. > This new property addresses this matter. > > 3. Add support to handle both inputs for nwl-dsi: DCSS and LCDIF Thanks. I've tested the drop-clock-level part with mxsfb on a Librem 5 devkit and it removes the slight flickering we've seen before (and which could be worked around by reducing the input pixel clock so 1 and 3 are Tested-by: Guido Günther <agx@xxxxxxxxxxx> I've have added some comments to the individual patches and try to get around to check out the DCSS part too. Cheers, -- Guido > > Laurentiu Palcu (1): > drm/bridge: nwl-dsi: add support for DCSS > > Robert Chiras (4): > drm/bridge: nwl-dsi: Add support for video_pll > dt-bindings: display/bridge: nwl-dsi: Document video_pll clock > drm/bridge: nwl-dsi: Add support for clock-drop-level > dt-bindings: display/bridge: nwl-dsi: Document fsl,clock-drop-level > property > > .../bindings/display/bridge/nwl-dsi.yaml | 7 + > drivers/gpu/drm/bridge/nwl-dsi.c | 338 ++++++++++++++++++++- > 2 files changed, 336 insertions(+), 9 deletions(-) > > -- > 2.7.4 >
